The throughput requirement of user equipment (UE) supporting standards such as 3GPP, LTE, and WiMAX is increasing with improvements in air interface technology. For example, category 4 UEs in LTE require downlink (DL) throughput of 150 Mbps and uplink (UL) throughput of 50 Mbps. The datapath of the MAC subsystem in such equipment, such as the implementation of the MAC layer in the broadband modems in UE, performs complex tasks in order to provide reliable and lossless data delivery to upper protocol layers. The MAC subsystem must meet strict Quality of Service (QoS) requirements under all operating conditions, including poor radio channel quality, handover operations, etc.
In order to meet the data throughput levels and QoS, the need for data packet or Protocol Data Unit (PDU) storage at the UE increases since the PDUs need to be buffered for retransmission of lost PDUs. As a result of advances in silicon processes and the availability of high-density on-chip memory modules, architectural considerations lead to the use of on-chip SRAM having a total size on the order of several megabytes as data packet/PDU storage. Although off-chip solutions are available, such as the use of external SDRAM, such architecture suffers from high power consumption and additional I/O pin counts for the memory interface. Moreover, when it comes to a few megabytes, which is relatively small size for standalone memories, it is difficult to find a cost-effective solution for building such an external memory.
Using embedded SRAM for data packet/PDU storage is an optimal solution in terms of power and system cost. Simulation results show, for example, that the total required buffer size for DL and UL corresponds to 520 KB for LTE category 4 UEs. The use of on-chip SRAM as a packet buffer has the benefit of incurring minimal delay associated with packet processing. Thus, on-chip SRAM can contribute to predictable system performance and optimal power consumption, which allows for the scalability of the system.